Sweep the data-flow wire and edge wording to input and source

This commit is contained in:
Dennis Kobert
2026-09-06 15:14:55 +00:00
parent 96521333d6
commit 9d3abe385f
34 changed files with 156 additions and 156 deletions

View File

@@ -128,7 +128,7 @@ fn node_registry() -> HashMap<ProtoNodeIdentifier, Vec<RegistryEntry>> {
.into_iter()
.map(|entry| (graphene_std::graphic::to_graphic::IDENTIFIER.clone(), entry)),
);
// The transitional level bridge: a leveled wire materializes into the legacy
// The transitional level bridge: a leveled input materializes into the legacy
// list an unconverted consumer expects. The rows are keyed under the legacy
// convert identifiers and die with the last legacy consumer.
node_types.extend(
@@ -367,7 +367,7 @@ mod tests {
}
}
/// One wire kind: every row consumes and produces record wires. A plain
/// One input kind: every row consumes and produces records. A plain
/// io type here would need a bridge adapter, and those are gone.
#[test]
fn every_registry_row_is_record_typed() {